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a29l004a series 512k x 8 bit cmos 3.0 volt-only, preliminary boot sector flash memory preliminary (march, 2005, version 0.0) amic technology, corp. document title 512k x 8 bit cmos 3.0 volt-onl y, boot sector flash memory revision history rev. history issue date remark 0.0 initial issue march 9, 2005 preliminary
a29l004a series 512k x 8 bit cmos 3.0 volt-only, preliminary boot sector flash memory preliminary (march, 2005, version 0.0) 1 amic technology, corp. features single power supply operation - full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications - regulated voltage range: 3.0 to 3.6 volt read and write operations for compatibility with high performance 3.3 volt microprocessors access times: - 70/90 (max.) current: - 4 ma typical active read current - 20 ma typical program/erase current - 200 na typical cmos standby - 200 na automatic sleep mode current flexible sector architecture - 16 kbyte/ 8 kbytex2/ 32 kb yte/ 64 kbytex7 sectors - any combination of sectors can be erased - supports full chip erase - sector protection: a hardware method of protecti ng sectors to prevent any inadvertent program or eras e operations within that sector. temporary sector unpr otect feature allows code changes in previously locked sectors unlock bypass program command - reduces overall programming time when issuing multiple program command sequence top or bottom boot block configurations available embedded algorithms - embedded erase algorithm wi ll automatically erase the entire chip or any combinati on of designated sectors and verify the erased sectors - embedded program algorithm automatically writes and verifies data at specified addresses typical 100,000 program/erase cycles per sector 20-year data retention at 125 c - reliable operation for t he life of the system compatible with jedec-standards - pinout and software compatible with single-power-supply flash memory standard - superior inadvertent write protection data polling and toggle bits - provides a software method of detecting completion of program or erase operations ready / busy pin (ry / by ) - provides a hardware method of detecting completion of program or erase operations (not available on 32-pin plcc & (s)tsop packages) erase suspend/erase resume - suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation hardware reset pin ( reset ) - hardware method to reset the device to reading array data (not available on 32 pin plcc & (s)tsop packages) package options - 40-pin tsop (forward type), 32-pin plcc or (s)tsop (forward type) general description the a29l004a is a 4mbit, 3.0 volt-only flash memory organized as 524,288 bytes of 8 bits. the 8 bits of data appear on i/o 0 - i/o 7 . the a29l004a is offered in 40-pin tsop, 32-pin plcc or (s)tsop packages. this device is designed to be programmed in-system with the standard system 3.0 volt vcc supply. additional 12.0 volt vpp is not required for in-system write or erase operations. however, the a29l004a can also be programmed in standard eprom programmers. the a29l004a has the first toggle bit, i/o 6 , which indicates whether an embedded program or erase is in progress, or it is in the erase suspend. besides the i/o 6 toggle bit, the a29l004a has a second toggle bit, i/o 2 , to indicate whether the addressed sector is being selected for erase. the a29l004a also offers the ability to program in the erase suspend mode. the standard a29l004a offers access times of 70 and 90ns, allowing high-speed microprocessors to operate without wait states. to eliminate bus contention the device has separate chip enable ( ce ), write enable ( we ) and output enable ( oe ) controls. the device requires only a single 3.0 volt power supply for both read and write functions. internally generated and regulated voltages are provid ed for the program and erase operations. the a29l004a is entirely software command set compatible with the jedec single-power-supply flash standard. commands are written to the command register using standard microprocessor write ti mings. register contents serve as input to an internal st ate-machine that controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by writing the proper program command sequence. this initiates the embedded program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin. device erasure occurs by executing the proper erase command sequence. this initiates the embedded erase algorithm - an internal algor ithm that automatically preprograms the array (if it is not already programmed) before executing the erase oper ation. during erase, the device automatically times the erase pulse widths and verifies proper erase margin. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. the host system can detect w hether a program or erase operation is complete by observing the ry / by pin (not
a29l004a series preliminary (march, 2005, version 0.0) 2 amic technology, corp. available on 32-pin plcc & (s)tsop), or by reading the i/o 7 ( data polling) and i/o 6 (toggle) status bits. after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. t he a29l004a is fully erased when shipped from the factory. the hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. this can be achieved via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other se ctor that is not selected for erasure. true background eras e can thus be achieved. the hardware reset pin terminates any operation in progress and resets the internal state machine to reading array data (not available on 32-pin plcc & (s)tsop). the reset pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the flash memory. the device offers two power-saving features. when addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. the system can also place the device into the standby mode. power consumption is greatly re duced in both these modes. pin configurations 40-pin tsop a29l004aw a15 a14 a13 a12 a11 a9 a8 reset nc ry/by a18 a7 a6 a5 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 i/o 0 nc vcc vcc i/o 4 i/o 5 i/o 6 i/o 7 a10 nc nc vss a17 a16 we i/o 1 i/o 2 i/o 3 23 22 21 a0 ce vss 24 oe a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 plcc 32-pin tsop (8mm x 20mm) 32-pin stsop (8mm x 13.4mm) 32-pin stsop (8mm x 14mm) a29l004av (8mm x 20mm) a29l004ax (8mm x 13.4mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a9 a8 a13 a14 a17 we vcc a16 a15 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a3 i/o 0 i/o 1 i/o 2 gnd i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ce a10 oe a11 a18 a2 a1 a0 a29l004al a7 a9 i/o 7 ce a6 a5 a4 a3 a2 a1 a0 i/o 0 a8 a13 a14 a12 a15 a16 a18 vcc we a17 i/o 1 i/o 2 gnd i/o 4 i/o 5 i/o 6 1 2 3 4 5 6 7 8 9 10 11 12 13 32 31 30 14 16 15 17 18 19 20 21 22 23 24 25 26 27 28 29 a11 oe a10 i/o 3 a29l004ay (8mm x 14mm)
a29l004a series preliminary (march, 2005, version 0.0) 3 amic technology, corp. block diagram pin descriptions pin no. description a0 - a18 address inputs i/o 0 - i/o 7 data inputs/outputs ce chip enable we write enable oe output enable reset hardware reset (n/a 32-pin plcc, (s)tsop) ry/ by ready/ busy - output (n/a 32-pin plcc, (s)tsop) vss ground vcc power supply nc pin not connected internally state control command register address latch x-decoder y-decoder chip enable output enable logic cell matrix y-gating vcc detector pgm voltage generator data latch input/output buffers erase voltage generator vcc vss we ce oe a0-a18 i/o 0 - i/o 7 timer stb stb reset sector switches ry/by (n/a 32-pin plcc, (s)tsop) (n/a 32-pin plcc, (s)tsop)
a29l004a series preliminary (march, 2005, version 0.0) 4 amic technology, corp. absolute maximum ratings* storage temperature plastic packages . ?? .0 c to + 70 c ambient temperature with power applied?? 0 c to + 70 c voltage with respect to ground vcc (note 1) . . . . . . . . . . . . . . . . . . . ?... . . . -0.5v to +4.0v a9, oe & reset (note 2) . . . . . . . . . . ?.. . -0.5 to +12.5v all other pins (note 1) . . . . . . . . . . . ?.. -0.5v to vcc + 0.5v output short circuit current (note 3) . . . . . . . ?.. ? 200ma notes: 1. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, input or i/o pins may undershoot vss to -2.0v for periods of up to 20ns. maximum dc voltage on input and i/o pins is vcc +0.5v. during voltage transitions, input or i/o pins may overshoot to vcc +2.0v for periods up to 20ns. 2. minimum dc input voltage on a9, oe and reset is - 0.5v. during voltage transitions, a9, oe and reset may overshoot vss to -2.0v for periods of up to 20ns. maximum dc input voltage on a9 is +12.5v which may overshoot to 14.0v for periods up to 20ns. ( reset is n/a on 32-pin plcc & (s)tsop) 3. no more than one output is s horted at a time. duration of the short circuit should not be greater than one second. *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the oper ational sections of these specification is not implie d or intended. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . ?.. . . . . . . 0 c to +70 c vcc supply voltages vcc for all devices . . . . . . . . . . . . . . . ?.. . . +2.7v to +3.6v operating ranges define t hose limits between which the functionally of the device is guaranteed. device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is composed of latches that st ore the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the st ate machine output s dictate the function of the device. the appr opriate device bus operations table lists the inputs and control levels required, and the resulting output. the following subsections describe each of these operations in further detail. table 1. a29l004a device bus operations operation ce oe we reset (n/a 32-pin plcc, (s)tsop) a0 ? a18 i/o 0 - i/o 7 read l l h h a in d out write l h l h a in d in cmos standby vcc 0.3 v x x vcc 0.3 v x high-z output disable l h h h x high-z hardware reset x x x l x high-z sector protect (see note 2) l h l v id sector address, a6=l, a1=h, a0=l d in sector unprotect (see note 2) l h l v id sector address, a6=h, a1=h, a0=l d in temporary sector unprotect x x x v id a in d in legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5v, x = don't care, d in = data in, d out = data out, a in = address in notes: 1. see the ?sector protection/unprot ection? section and temporary sector unprotect for more information. 2. this function is not availabl e on 32-pin plcc & (s)tsop packages.
a29l004a series preliminary (march, 2005, version 0.0) 5 amic technology, corp. requirements for reading array data to read array data from the outputs, the system must drive the ce and oe pins to v il . ce is the power control and selects the device. oe is the output control and gates array data to the output pins. we should remain at v ih all the time during read operation. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see "reading array data" for more information. refer to the ac read operations table for timing specifications and to the read operations timings diagram for the timing waveforms, l cc1 in the dc characteristics table represents the active current specification for reading array data. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we and ce to v il , and oe to v ih . the device features an unlock bypass mode to facilitate faster programming. once the device enters the unlock bypass mode, only two write cycles are required to program a byte, instead of four. the ?byte program command sequence? section has details on programming data to the device using both standard and unlock bypass command sequence. an erase operation can erase one sector, multiple sectors, or the entire device. the sector address tables indicate the address range that each sector occupies. a "sector address" consists of the address inputs required to uniquely select a sector. see the "comm and definitions" section for details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on i/o 7 - i/o 0 . standard read cycle timings apply in this mode. refer to the "autoselect mode" and "autoselect command sequence" sections for more information. i cc2 in the dc characteristics table represents the active current specification for the write mode. the "ac characteristics" section contains timing specification tables and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on i/o 7 - i/o 0 . standard read cycle timings and i cc read specifications apply. refer to "write operation status" for more information, and to each ac characteristics section for timing diagrams. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe input. the device enters the cmos standby mode when the ce & reset pins ( ce only on 32-pin plcc & (s)tsop packages) are both held at vcc 0.3v. (note that this is a more restricted voltage range than v ih .) if ce and reset (n/a on 32-pin plcc & (s)tsop packages) are held at v ih , but not within vcc 0.3v, the device will be in the standby mode, but the standby current will be greater. the device requires the standard access time (t ce ) before it is ready to read data. if the device is deselected during erasure or programming, the device draws active current until the operation is completed. i cc3 and i cc4 in the dc characteristics tables represent the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc +30ns. the automatic sleep mode is independent of the ce , we and oe control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc4 in the dc characteristics table represents the automatic sleep mode current specification. output disable mode when the oe input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state. reset : hardware reset pin (n/a on 32-pin plcc & (s)tsop packages) the reset pin provides a hardware method of resetting the device to reading array data. when the system drives the reset pin low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the reset pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset pulse. when reset is held at vss 0.3v, the device draws cmos standby current (i cc4 ). if reset is held at v il but not within vss 0.3v, the standby current will be greater. the reset pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory. if reset is asserted during a program or erase operation, the ry/ by pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time t ready (during embedded algorithms). the system can thus monitor ry/ by to determine whether the reset operation is complete. if reset is asserted when a program or erase operation is not executing (ry/ by pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algorithms). the system can read data t rh after the reset pin return to v ih . refer to the ac charac teristics tables for reset parameters and diagram.
a29l004a series preliminary (march, 2005, version 0.0) 6 amic technology, corp. table 2. a29l004a top boot block sector address table sector a18 a17 a16 a15 a14 a13 sector size (kbytes) address range (in hexadecimal) sa0 0 0 0 x x x 64 00000h - 0ffffh sa1 0 0 1 x x x 64 10000h - 1ffffh sa2 0 1 0 x x x 64 20000h - 2ffffh sa3 0 1 1 x x x 64 30000h - 3ffffh sa4 1 0 0 x x x 64 40000h - 4ffffh sa5 1 0 1 x x x 64 50000h - 5ffffh sa6 1 1 0 x x x 64 60000h - 6ffffh sa7 1 1 1 0 x x 32 70000h - 77fffh sa8 1 1 1 1 0 0 8 78000h - 79fffh sa9 1 1 1 1 0 1 8 7a000h - 7bfffh sa10 1 1 1 1 1 x 16 7c000h - 7ffffh table 3. a29l004a bottom boot block sector address table sector a18 a17 a16 a15 a14 a13 sector size (kbytes) address range (in hexadecimal) sa0 0 0 0 0 0 x 16 00000h - 03fffh sa1 0 0 0 0 1 0 8 04000h - 05fffh sa2 0 0 0 0 1 1 8 06000h - 07fffh sa3 0 0 0 1 x x 32 08000h - 0ffffh sa4 0 0 1 x x x 64 10000h - 1ffffh sa5 0 1 0 x x x 64 20000h - 2ffffh sa6 0 1 1 x x x 64 30000h - 3ffffh sa7 1 0 0 x x x 64 40000h - 4ffffh sa8 1 0 1 x x x 64 50000h - 5ffffh sa9 1 1 0 x x x 64 60000h - 6ffffh sa10 1 1 1 x x x 64 70000h - 7ffffh
a29l004a series preliminary (march, 2005, version 0.0) 7 amic technology, corp. autoselect mode the autoselect mode provid es manufacturer and device identification, and sector pr otection verification, through identifier codes output on i/o 7 - i/o 0 . this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in autoselect codes (high voltage method) table. in addition, when verifying sector protection, th e sector address must appear on the appropriate highest order address bits. refer to the corresponding sector address tables. the command definitions table shows the remaining address bits that are don't care. when all necessary bits have been set as required, the programming equipment may then read the corresponding identifier code on i/o 7 - i/o 0 .to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in the command definitions tabl e. this method does not require v id . see "command definitions" for details on using the autoselect mode. table 4. a29l004a autoselect codes (high voltage method) description ce oe we a18 to a13 a12 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 i/o 7 to i/o 0 manufacturer id: amic l l h x x v id x l x l l 37h device id: a29l004a (top boot block) l l h x x v id x l x l h 34h device id: a29l004a (bottom boot block) l l h x x v id x l x l h b5h continuation id l l h x x v id x l x h h 7fh 01h (protected) sector protection verification l l h sa x v id x l x h l 00h (unprotected) l=logic low= v il , h=logic high=v ih , sa=sector address, x=don?t care. note: the autoselect codes may also be accessed in-system via command sequences.
a29l004a series preliminary (march, 2005, version 0.0) 8 amic technology, corp. sector protection/unprotection the hardware sector protec tion feature disables both program and erase operations in any sector. the hardware sector unprotection feature re-enables both program and erase operations in previ ously protected sectors. it is possible to determine whether a sector is protected or unprotected. see ?autoselect mode? for details. sector protection / unprotecti on can be implemented via two methods. the primary method requires vid on the reset pin only (n/a on 32-pin plcc & (s)tsop packages), and can be implemented either in-system or via programming equipment. figure 2 shows the algorithm and the sector protect / unprotect timing diagram illustrates the timing waveforms for this feature. this method uses standard microprocessor bus cycle timing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method must be implemented using programmi ng equipment. the procedure requires a high voltage (v id ) on address pin a9 and the control pins. the device is shipped with all sectors unprotected. it is possible to determine whether a sector is protected or unprotected. see "autoselect mode" for details. hardware data protection the requirement of command unlocking sequence for programming or erasing provi des data protection against inadvertent writes (refer to the command definitions table). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up transitions, or from system noise. the device is powered up to read array data to avoid accidentally writing data to the array. write pulse "glitch" protection noise pulses of less than 5ns (typical) on oe , ce or we do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe =v il , ce = v ih or we = v ih . to initiate a write cycle, ce and we must be a logical zero while oe is a logical one. power-up write inhibit if we = ce = v il and oe = v ih during power up, the device does not accept commands on the rising edge of we . the internal state machine is automatically reset to reading array data on the initial power-up. temporary sector unprotect (n/a on 32-pin plcc & (s)tsop packages) this feature allows temporar y unprotection of previous protected sectors to change data in-system. the sector unprotect mode is activated by setting the reset pin to v id . during this mode, formerl y protected sectors can be programmed or erased by select ing the sector addresses. once v id is removed from the reset pin, all the previously protected sectors are protect ed again. figure 1 shows the algorithm, and the temporary sector unprotect diagram shows the timing waveforms, for this feature. start reset = v id (note 1) perform erase or program operations reset = v ih temporary sector unprotect completed (note 2) notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. figure 1. temporary sector unprotect operation
a29l004a series preliminary (march, 2005, version 0.0) 9 amic technology, corp. start plscnt=1 reset=v id wait 1 us first write cycle=60h? set up sector address sector protect write 60h to sector address with a6=0, a1=1, a0=0 wait 150 us verify sector protect: write 40h to sector address with a6=0, a1=1, a0=0 read from sector address with a6=0, a1=1, a0=0 data=01h? protect another sector? remove v id from reset write reset command sector protect complete sector protect algorithm temporary sector unprotect mode increment plscnt plscnt =25? device failed no no no yes reset plscnt=1 yes yes no protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address start plscnt=1 reset=v id wait 1 us first write cycle=60h? no temporary sector unprotect mode yes no all sectors protected? set up first sector address sector unprotect: write 60h to sector address with a6=1, a1=1, a0=0 wait 15 ms verify sector unprotect : write 40h to sector address with a6=1, a1=1, a0=0 read from sector address with a6=1, a1=1, a0=0 data=00h? last sector verified? remove v id from reset write reset command sector unprotect complete yes yes set up next sector address no yes yes sector unprotect algorithm increment plscnt plscnt= 1000? device failed yes no no figure 2. in-system sector protect/unprotect algorithms
a29l004a series preliminary (march, 2005, version 0.0) 10 amic technology, corp. command definitions writing specific address and data commands or sequences into the command register initiates device operations. the command definitions table defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we or ce , whichever happens later. all data is latched on the rising edge of we or ce , whichever happens first. refer to the appropriate timing diagrams in the "ac characteristics" section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see "erase suspend/erase resume commands" for more information on this mode. the system must issue the reset command to re-enable the device for reading array data if i/o 5 goes high, or while in the autoselect mode. see the "reset command" section, next. see also "requirements for reading array data" in the "device bus operations" section for more information. the read operations table provi des the read parameters, and read operation timings diagram shows the timing diagram. reset command writing the reset command to t he device resets the device to reading array data. address bits are don't care for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if i/o 5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. the command definitions table shows the address and data requirements. this method is an alternative to that shown in the autoselect codes (high voltage method) table, which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. the device then enters the autoselec t mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufacturer code and another read cycle at xx03h retrieves the continuation code. a read cycle at address xx01h returns the device code. a read cycle contai ning a sector address (sa) and the address 02h in returns 01h if that sector is protected, or 00h if it is unprotected. refe r to the sector address tables for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. byte program command sequence programming is a four-bus-cyc le operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al gorithm. the system is not required to provide further controls or timings. the device automatically provides internal ly generated program pulses and verify the programmed cell margin. table 5 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are longer latched. the system c an determine the st atus of the program operation by using i/o 7 , i/o 6 , or ry/ by (n/a on 32- pin plcc & (s)tsop packages). see ?write operation status? for information on these status bits. any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset immediately terminates the progr amming operation. the byte program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a ?0? back to a ?1?. attempting to do so may hal t the operat ion and set i/o5 to ?1?, or cause the data polling algorithm to indicate the operation was successful. howe ver, a succeeding read will show that the data is still ?0 ?. only erase operations can convert a ?0? to a ?1?.
a29l004a series preliminary (march, 2005, version 0.0) 11 amic technology, corp. start write program command sequence data poll from system verify data ? last address ? programming completed no yes yes increment address embedded program algorithm in progress note : see the appropriate command definitions table for program command sequence. figure 3. program operation unlock bypass command sequence the unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then enters the unlock bypass mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program command, a0h; the second cycle contains the program address and data. additi onal data is programmed in the same manner. this mode di spenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. table 5 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock bypass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, t he system must issue the two- cycle unlock bypass reset command sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are don?t care for both cycle. the device returns to reading array data. figure 3 illustrates the algorithm for the program operation. see the erase/program operations in ?ac characteristics? for parameters, and to program operation timings for timing diagrams. chip erase command sequence chip erase is a six-bus-cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the command definitions table shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embedded erase algorithm are ignored. the system can determine the status of the erase operation by using i/o 7 , i/o 6 , or i/o 2 . see "write operation status" for in formation on these status bits. when the embedded erase algorit hm is complete, the device returns to reading array data and addresses are no longer latched. figure 4 illustrates the algorith m for the erase operation. see the erase/program operations t ables in "ac characteristics" for parameters, and to the ch ip/sector erase operation timings for timing waveforms. sector erase command sequence sector erase is a six-bus-cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. the command definitions table shows the address and data requirements for the sector erase command sequence. the device does not require t he system to preprogram the memory prior to erase. the embedded erase algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is wr itten, a sector erase time- out of 50 s begins. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sector erase buffer may be done in any sequence, and the number of se ctors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor i/o 3 . any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands.
a29l004a series preliminary (march, 2005, version 0.0) 12 amic technology, corp. start write erase command sequence data poll from system data = ffh ? erasure completed yes embedded erase algorithm in progress note : 1. see the appropriate command definitions table for erase command sequences. 2. see "i/o 3 : sector erase timer" for more information. no figure 4. erase operation the system can monitor i/o 3 to determine if the sector erase timer has timed out. (see the " i/o 3 : sector erase timer" section.) the time-out begins fr om the rising edge of the final we pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. when the embedded erase algorit hm is complete, the device returns to reading array data and addresses are no longer latched. the system can dete rmine the status of the erase operation by using i/o 7 , i/o 6 , or i/o 2 . refer to "write operation status" for informati on on these status bits. 4 illustrates the algorithm for the erase operation. refer to the erase/program operati ons tables in the "ac characteristics" section for parameters, and to the sector erase operations timing diagram for timing waveforms. erase suspend/erase resume commands the erase suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period duri ng the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. writing the erase suspend command during the sector er ase time-out immediately terminates the time-out period and suspends the erase operation. addresses are "don't cares" when writing the erase suspend command. when the erase suspend command is written during a sector erase operation, the device requires a maximum of 20 s to suspend the erase operation. however, when the erase suspend command is wri tten during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation ha s been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device "erase suspends" all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sector s produces status data on i/o 7 - i/o 0 . the system can use i/o 7 , or i/o 6 and i/o 2 together, to determine if a sector is ac tively erasing or is erase- suspended. see "write operat ion status" for information on these status bits. after an erase-suspended program operation is complete, the system can once again read array data within non- suspended sectors. the system can determine the status of the program operation using the i/o 7 or i/o 6 status bits, just as in the standard program o peration. see "write operation status" for more information. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device re verts to the erase suspend mode, and is ready for anot her valid operation. see "autoselect command sequence" for more information. the system must write the erase resume command (address bits are "don't care") to exit the erase suspend mode and continue the sector er ase operation. further writes of the resume command ar e ignored. another erase suspend command can be written after the device has resumed erasing.
a29l004a series preliminary (march, 2005, version 0.0) 13 amic technology, corp. table 5. a29l004a command definitions bus cycles (notes 2 - 5) first second third fourth fifth sixth command sequence (note 1) cycles addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 manufacturer id 4 555 aa 2aa 55 555 90 x00 37 device id, top boot block 4 555 aa 2aa 55 555 90 x01 34 device id, bottom boot block 4 555 aa 2aa 55 555 90 x01 b5 continuation id 4 555 aa 2aa 55 555 90 x03 7f xx00 autoselect (note 8) sector protect verify (note 9) 4 555 aa 2aa 55 555 90 (sa) x02 xx01 program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 10) 2 xxx a0 pa pd unlock bypass reset (note 11) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 12) 1 xxx b0 erase resume (note 13) 1 xxx 30 legend: x = don't care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be prog rammed. addresses latch on the falling edge of the we or ce pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we or ce pulse, whichever happens first. sa = address of the sector to be verified (in autoselect mode ) or erased. address bits a18 - a13 select a unique sector. note: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operation. 4. address bits a18 - a11 are don't cares for unlock and command cycles, unless sa or pa required. 5. no unlock or command cycles required when reading array data. 6. the reset command is required to return to reading arra y data when device is in the autoselect mode, or if i/o 5 goes high (while the device is providing status data). 7. the fourth cycle of the autoselec t command sequence is a read cycle. 8. the data is 00h for an unprotec ted sector and 01h for a prot ected sector. see ?autoselec t command sequence? for more information. 9. the unlock bypass command is required prior to the unlock bypass program command. 10. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 11. the system may read and program in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. 12. the erase resume command is valid only during the erase suspend mode.
a29l004a series preliminary (march, 2005, version 0.0) 14 amic technology, corp. write operation status several bits, i/o 2 , i/o 3 , i/o 5 , i/o 6 , i/o 7, ry/ by are provided in the a29l004a to determine the status of a write operation (ry/ by pin is not available on 32-pin plcc & (s)tsop packages). table 6 and the following subsections describe the functions of these status bits. i/o 7 , i/o 6 and ry/ by each offer a method for determining whether a program or erase operation is complete or in pr ogress. these three bits are discussed first. i/o 7 : data polling the data polling bit, i/o 7 , indicates to the host system whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data polling is valid after the rising edge of the final we pulse in the program or erase command sequence. during the embedded program algorithm, the device outputs on i/o 7 the complement of the datum programmed to i/o 7 . this i/o 7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to i/o 7 . the system must provide the program address to read valid status information on i/o 7 . if a program address falls within a protected sector, data polling on i/o 7 is active for approximately 2 s, then the device returns to reading array data. during the embedded erase algorithm, data polling produces a "0" on i/o 7 . when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data polling produces a "1" on i/o 7 .this is analogous to the complement/true datum output described for the embedded program algorithm: the erase func tion changes all the bits in a sector to "1"; prior to this, the device outputs the "complement," or "0." the sy stem must provide an address within any of the sectors sele cted for erasure to read valid status information on i/o 7 . after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on i/o 7 is active for approximately 100 s, then the device returns to reading array data. if not all sele cted sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects i/o 7 has changed from the complement to true data, it can read valid data at i/o 7 - i/o 0 on the following read cycles. this is because i/o 7 may change asynchronously with i/o 0 - i/o 6 while output enable ( oe ) is asserted low. the data polling timings (during embedded algorithms) in the "ac characteristics" section illustrates this. table 6 shows the outputs for data polling on i/o 7 . figure 5 shows the data polling algorithm. start read i/o 7 -i/o 0 address = va i/o 7 = data ? fail no note : 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. i/o 7 should be rechecked even if i/o 5 = "1" because i/o 7 may change simultaneously with i/o 5 . no read i/o 7 - i/o 0 address = va i/o 5 = 1? i/o 7 = data ? yes no pass yes yes figure 5. data polling algorithm
a29l004a series preliminary (march, 2005, version 0.0) 15 amic technology, corp. ry/ by : read/ busy (n/a on 32-pin plcc & (s)tsop packages) the ry/ by is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/ by status is valid after the rising edge of the final we pulse in the command sequence. since ry/ by is an open-drain output, several ry/ by pins can be tied together in parallel with a pull-up resistor to vcc. if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (including during the erase suspend mode), or is in the standby mode. table 6 shows the outputs for ry/ by . refer to ? reset timings?, ?timing waveforms for program operation? and ?timing waveforms for chip/sector erase operation? for more information. i/o 6 : toggle bit i toggle bit i on i/o 6 indicates whether an embedded program or erase algorithm is in progre ss or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause i/o 6 to toggle. (the system may use either oe or ce to control the read cycles.) when the operation is complete, i/o 6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, i/o 6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotec ted sectors, and ignores the selected sectors that are protected. the system can use i/o 6 and i/o 2 together to determine whether a sector is actively er asing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), i/o 6 toggles. when the device enters the erase suspend mode, i/o 6 stops toggling. however, the system must also use i/o 2 to determine which sectors are erasing or erase- suspended. alternatively, the system can use i/o 7 (see the subsection on " i/o 7 : data polling"). if a program address falls within a protected sector, i/o 6 toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. i/o 6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. the write operatio n status table sh ows the outputs for toggle bit i on i/o 6 . refer to figure 6 for the toggle bit algorithm, and to the toggle bit timings figure in the "ac characteristics" section for the timing diagram. the i/o 2 vs. i/o 6 figure shows the differences between i/o 2 and i/o 6 in graphical form. see also the subsection on " i/o 2 : toggle bit ii". i/o 2 : toggle bit ii the "toggle bit ii" on i/o 2 , when used with i/o 6 , indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we pulse in the command sequence. i/o 2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe or ce to control the read cycles.) but i/o 2 cannot distinguish wh ether the sector is actively erasing or is erase-suspended. i/o 6 , by comparison, indicates whether the device is acti vely erasing, or is in erase suspend, but cannot distingu ish which sectors are selected for erasure. thus, both status bi ts are required for sector and mode information. refer to table 6 to compare outputs for i/o 2 and i/o 6 . figure 6 shows the toggle bit algorithm in flowchart form, and the section " i/o 2 : toggle bit ii" explains the algorithm. see also the " i/o 6 : toggle bit i" subsection. refer to the toggle bit timings figure for the toggle bit timing diagram. the i/o 2 vs. i/o 6 figure shows the differences between i/o 2 and i/o 6 in graphical form. reading toggle bits i/o 6 , i/o 2 refer to figure 6 for the following discussion. whenever the system initially begins reading toggle bit status, it must read i/o 7 - i/o 0 at least twice in a row to determine whether a toggle bit is toggling. typica lly, a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the progr am or erase operation. the system can read array data on i/o 7 - i/o 0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of i/o 5 is high (see the section on i/o 5 ). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as i/o 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or eras e operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and i/o 5 has not gone high. the system may continue to monitor the toggle bit and i/o 5 through successive read cycles, determining the status as described in the previous paragr aph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginni ng of the algorithm when it returns to determine the status of the operation (top of figure 6). i/o 5 : exceeded timing limits i/o 5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions i/o 5 produces a "1." this is a failure condition that indicates the program or erase cycle was not successfully completed. the i/o 5 failure condition may appear if the system tries to program a "1 "to a location that is previously programmed to "0." only an erase operation can change a "0" back to a "1." under this condition, the device halts the operation, and when the operation has exc eeded the timing limits, i/o 5 produces a "1." under both these conditions, the system must issue the reset command to re turn the device to reading array data.
a29l004a series preliminary (march, 2005, version 0.0) 16 amic technology, corp. i/o 3 : sector erase timer after writing a sector erase command sequence, the system may read i/o 3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out is complete, i/o 3 switches from "0" to "1." the system may ignore i/o 3 if the system can g uarantee that the time between additional sector erase commands will always be less than 50 s. see also the "sector erase command sequence" section. after the sector erase command sequence is written, the system should read the status on i/o 7 ( data polling) or i/o 6 (toggle bit i) to ensure the device has accepted the command sequence, and then read i/o 3 . if i/o 3 is "1", the internally controlled erase cycle has begun; all further commands (other than erase suspend) are ignored until the erase operation is complete. if i/o 3 is "0", the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of i/o 3 prior to and following each subsequent sector erase command. if i/o 3 is high on the second status check, the la st command might not have been accepted. table 6 shows the outputs for i/o 3 . start read i/o 7 -i/o 0 toggle bit = toggle ? program/erase operation not commplete, write reset command yes notes : 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as i/o 5 changes to "1". see text. no read i/o 7 - i/o 0 twice i/o 5 = 1? toggle bit = toggle ? yes yes program/erase operation complete no no read i/o 7 -i/o 0 (notes 1,2) figure 6. toggle bit algorithm (note 1)
a29l004a series preliminary (march, 2005, version 0.0) 17 amic technology, corp. table 6. write operation status i/o 7 i/o 6 i/o 5 i/o 3 i/o 2 ry/ by operation (note 1) (note 2) (note 1) (n/a on 32-pin plcc & (s)tsop packages) embedded program algorithm 7 i/o toggle 0 n/a no toggle 0 standard mode embedded erase algorithm 0 toggle 0 1 toggle 0 reading within erase suspended sector 1 no toggle 0 n/a toggle 1 reading within non-erase suspended sector data data data data data 1 erase suspend mode erase-suspend-program 7 i/o toggle 0 n/a n/a 0 notes: 1. i/o 7 and i/o 2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. i/o 5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. see ?i/o 5 : exceeded timing limits? for more information. maximum negative input overshoot 20ns 20ns 20ns +0.8v -0.5v -2.0v maximum positive input overshoot 20ns 20ns 20ns vcc+0.5v 2.0v vcc+2.0v
a29l004a series preliminary (march, 2005, version 0.0) 18 amic technology, corp. dc characteristics cmos compatible parameter symbol parameter description test description min. typ. max. unit i li input load current v in = vss to vcc. vcc = vcc max 1.0 a i lit a9 input load current vcc = v cc max, a9 =12.5v 35 a i lo output leakage current v out = vss to vcc. vcc = vcc max 1.0 a 5 mhz 4 10 i cc1 vcc active read current (notes 1, 2) ce = v il , oe = v ih 1 mhz 2 4 ma i cc2 vcc active write (program/erase) current (notes 2, 3, 4) ce = v il , oe =v ih 20 30 ma i cc3 vcc standby current (note 2) ce = v ih , reset = vcc 0.3v 1 5 a i cc4 vcc standby current during reset (note 2) (n/a on 32-pin plcc & (s)tsop packages) reset = vss 0.3v 1 5 a i cc5 automatic sleep mode (note 2, 4, 5) v ih = vcc 0.3v ; v il = vss 0.3v 1 5 a v il input low level -0.5 0.8 v v ih input high level 0.7 x vcc vcc + 0.3 v v id voltage for autoselect and temporary unprotect sector vcc = 3.3 v 11.5 12.5 v v ol output low voltage i ol = 4.0ma, vcc = vcc min 0.45 v v oh1 i oh = -2.0 ma, vcc = vcc min 0.85 x vcc v v oh2 output high voltage i oh = -100 a, vcc = vcc min vcc - 0.4 v notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe at v ih . typical vcc is 3.0v. 2. maximum i cc specifications are tested with vcc = vcc max. 3. i cc active while embedded algorithm (program or erase) is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30ns. typical sleep mode current is 1 a. 5. not 100% tested.
a29l004a series preliminary (march, 2005, version 0.0) 19 amic technology, corp. dc characteristics (continued) zero power flash 0 500 1000 1500 2000 2500 3000 3500 4000 5 0 10 15 20 25 time in ns supply current in ma note: addresses are switching at 1mhz i cc1 current vs. time (showing active and automatic sleep currents) 12345 0 2 4 6 8 10 frequency in mhz supply current in ma c 25 t : note = typical i cc1 vs. frequency 3.6v 2.7v
a29l004a series preliminary (march, 2005, version 0.0) 20 amic technology, corp. ac characteristics read only operations parameter symbols speed jedec std description test setup -70 -90 unit t avav t rc read cycle time (note 1) min. 70 90 ns t avqv t acc address to output delay ce = v il oe = v il max. 70 90 ns t elqv t ce chip enable to output delay oe = v il max. 70 90 ns t glqv t oe output enable to output delay max. 30 35 ns read min. 0 0 ns t oeh output enable hold time (note 1) toggle and data polling min. 10 10 ns t ehqz t df chip enable to output high z (notes 1) max. 25 30 ns t ghqz t df output enable to output high z (notes 1) 25 30 ns t axqx t oh output hold time from addresses, ce or oe , whichever occurs first (note 1) min. 0 0 ns notes: 1. not 100% tested. 2. see test conditions and test setup for test specifications. timing waveforms for read only operation addresses addresses stable ce oe we output valid high-z output t rc t oeh t oe t ce high-z t oh t df t acc 0v reset ry/by
a29l004a series preliminary (march, 2005, version 0.0) 21 amic technology, corp. ac characteristics hardware reset ( reset , n/a on 32-pin plcc & (s)tsop packages) parameter jedec std description test setup all speed options unit t ready reset pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rb ry/ by recovery time min 0 ns t rpd reset low to standby mode min 20 s note: not 100% tested. reset timings ce, oe reset t rh t rp t ready reset timings not during embedded algorithms reset t rp ~ ~ reset timings during embedded algorithms ry/by ~ ~ t rb ~ ~ t ready ce, oe ry/by
a29l004a series preliminary (march, 2005, version 0.0) 22 amic technology, corp. temporary sector unprotect (n/a on 32-pin plcc & (s)tsop packages) parameter jedec std description all speed options unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset setup time for temporary sector unprotect min 4 s note: not 100% tested. temporary sector unprotect timing diagram program or erase command sequence reset ~ ~ ~ ~ ~ ~ 12v 0 or 3v t vidr t vidr 0 or 3v t rsp ce we ry/by ~ ~
a29l004a series preliminary (march, 2005, version 0.0) 23 amic technology, corp. ac characteristics erase and program operations parameter speed jedec std description -70 -90 unit t avav t wc write cycle time (note 1) min. 70 90 ns t avwl t as address setup time min. 0 ns t wlax t ah address hold time min. 45 45 ns t dvwh t ds data setup time min. 35 45 ns t whdx t dh data hold time min. 0 ns t oes output enable setup time min. 0 ns t ghwl t ghwl read recover time before write ( oe high to we low) min. 0 ns t elwl t cs ce setup time min. 0 ns t wheh t ch ce hold time min. 0 ns t wlwh t wp write pulse width min. 35 35 ns t whwl t wph write pulse width high min. 30 ns t whwh1 t whwh1 byte programming operation (note 2) typ. 17 s t whwh2 t whwh2 sector erase operatio n (note 2) typ. 1 sec t vcs vcc set up time (note 1) min. 50 s t rb recovery time from ry/ by (n/a on 32-pin plcc & (s)tsop packages) min 0 ns t busy program/erase valid to ry/ by delay (n/a on 32-pin plcc & (s)tsop packages ) min 90 ns notes: 1. not 100% tested. 2. see the "erase and programming perfo rmance" section for more information.
a29l004a series preliminary (march, 2005, version 0.0) 24 amic technology, corp. timing waveforms for program operation addresses ce oe we data vcc a0h pd t wc pa program command sequence (last two cycles) pa d out ~ ~ ~ ~ pa ~ ~ status ~ ~ ~ ~ ~ ~ ~ ~ t as t vcs read status data (last two cycles) 555h t ah t whwh1 t ch t wp t wph t cs t ds t dh note : 1. pa = program addrss, pd = program data, dout is the true data at the program address. 2. illustration shows device in word mode. ~ ~ t rb t busy ry/by
a29l004a series preliminary (march, 2005, version 0.0) 25 amic technology, corp. addresses ce oe we data vcc 55h 30h t wc sa erase command sequence (last two cycles) va complete ~ ~ ~ ~ va ~ ~ in progress ~ ~ ~ ~ ~ ~ ~ ~ t as t vcs read status data 2aah t ah t whwh2 t ch t wp t wph t cs t ds t dh note : 1. sa = sector address (for sector erase), va = valid address for reading status data (see "write operaion ststus"). 2. illustratin shows device in word mode. 555h for chip erase 10h for chip erase ~ ~ t rb t busy ry/by timing waveforms for chip/sector erase operation
a29l004a series preliminary (march, 2005, version 0.0) 26 amic technology, corp. timing waveforms for data polling (during embedded algorithms) timing waveforms for toggle bit (during embedded algorithms) note: va = valid address; not required for i/o 6 . illustration shows first two status cy cle after command sequence, last status read cycle, and array data read cycle. addresses ce oe we i/o 7 t rc va va va ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ complement ~ ~ complement true valid data high-z status data ~ ~ status data true valid data high-z i/o 0 - i/o 6 t ac c t ce t ch t oe t oeh t df t oh note : va = valid address. illustation shows first status cycle after command sequence, last status read cycle, and array data read cycle. ~ ~ t busy ry/by high-z addresses ce oe we i/o 6 , i/o 2 t rc va va va ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ valid status t ac c t ce t ch t oe t oeh t df t oh va valid status valid status valid data ~ ~ (first read) (second read) (stop togging) ry/by ~ ~ t busy high-z
a29l004a series preliminary (march, 2005, version 0.0) 27 amic technology, corp. timing waveforms for sector protect/unprotect v id note : for sector protect, a6=0, a1=1, a0=0. for sector unprotect, a6=1, a1=1, a0=0 ~ ~ ~ ~ ~ ~ ~ ~ v ih reset sa, a6, a1, a0 data ce we oe valid* valid* valid* 60h 60h 40h status sector protect/unprotect verify 1us sector protect:150us sector unprotect:15ms timing waveforms for i/o 2 vs. i/o 6 enter embedded erasing erase suspend enter erase suspend program erase resume we i/o 6 i/o 2 erase erase suspend read erase suspend read erase erase complete i/o 2 and i/o 6 toggle with oe and ce note : both i/o 6 and i/o 2 toggle with oe or ce. see the text on i/o 6 and i/o 2 in the section "write operation status" for more information. ~ ~ ~ ~ ~ ~ erase suspend program ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
a29l004a series preliminary (march, 2005, version 0.0) 28 amic technology, corp. ac characteristics erase and program operations alternate ce controlled writes parameter speed jedec std description -70 -90 unit t avav t wc write cycle time (note 1) min. 70 90 ns t avel t as address setup time min. 0 ns t elax t ah address hold time min. 45 45 ns t dveh t ds data setup time min. 35 45 ns t ehdx t dh data hold time min. 0 ns t oes output enable setup time min. 0 ns t ghel t ghel read recover time before write ( oe high to we low) min. 0 ns t wlel t ws we setup time min. 0 ns t ehwh t wh we hold time min. 0 ns t eleh t cp ce pulse width min. 35 35 ns t ehel t cph ce pulse width high min. 30 ns t whwh1 t whwh1 byte programming operation (note 2) typ. 17 s t whwh2 t whwh2 sector erase operatio n (note 2) typ. 1 sec notes: 1. not 100% tested. 2. see the "erase and programming perfo rmance" section for more information.
a29l004a series preliminary (march, 2005, version 0.0) 29 amic technology, corp. timing waveforms for alternate ce controlled write operation addresses we oe ce data 555 for program 2aa for erase pa d out ~ ~ ~ ~ i/o 7 ~ ~ ~ ~ ~ ~ data polling note : 1. pa = program address, pd = program data, sa = sector address, i/o 7 = complement of data input, d out = array data. 2. figure indicates the last two bus cycles of the command sequence. pd for program 30 for sector erase 10 for chip erase ~ ~ t busy t whwh1 or 2 t ah t as t wc t wh t cp t ws t cph pa for program sa for sector erase 555 for chip erase a0 for program 55 for erase t rh t ds t dh ~ ~ ~ ~ reset ry/by erase and programming performance parameter typ. (note 1) max. (note 2) unit comments sector erase time 1 8 sec chip erase time 11 64 sec excludes 00h programming prior to erasure byte programming time 17 200 s chip programming time (note 3) 6 13.5 sec excludes system-level overhead (note 5) notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0v vcc, 10,000 cycles. additionally, programming typically assumes checkerboard pattern. 2. under worst case conditions of 90 c, vcc = 2.7v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum byte program time listed. if t he maximum byte program time given is exceeded, only then does the device set i/o 5 = 1. see the section on i/o 5 for further information. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the four-bus-cycle command sequence for programming. see table 5 for further information on command definitions. 6. the device has a guaranteed minimum erase an d program cycle endurance of 10,000 cycles.
a29l004a series preliminary (march, 2005, version 0.0) 30 amic technology, corp. latch-up characteristics description min. max. input voltage with respect to vss on all i/o pins -1.0v vcc+1.0v vcc current -100 ma +100 ma input voltage with respect to vss on all pins except i/o pins (including a9, oe and reset ) -1.0v 12.5v includes all pins except vcc. test conditions: vcc = 3.0v, one pin at time. tsop pin capacitance parameter symbol parameter description test setup typ. max. unit c in input capacitance v in =0 6 7.5 pf c out output capacitance v out =0 8.5 12 pf c in2 control pin capacitance v in =0 7.5 9 pf notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0mhz plcc pin capacitance parameter symbol parameter description test setup typ. max. unit c in input capacitance v in =0 4 6 pf c out output capacitance v out =0 8 12 pf c in2 control pin capacitance v pp =0 8 12 pf notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0mhz data retention parameter test conditions min unit 150 c 10 years minimum pattern data retention time 125 c 20 years
a29l004a series preliminary (march, 2005, version 0.0) 31 amic technology, corp. test conditions test specifications test condition -70 -90 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 5 ns input pulse levels 0. 0 - 3.0 0.0 - 3.0 v input timing measurement re ference levels 1.5 1.5 v output timing measurement re ference levels 1.5 1.5 v test setup 6.2 k ? device under test c l diodes = in3064 or equivalent 2.7 k ? 3.3 v
a29l004a series preliminary (march, 2005, version 0.0) 32 amic technology, corp. ordering information top boot sector flash part no. access time (ns) active read current typ. (ma) program/erase current typ. (ma) standby current typ. ( a ) package a29l004atl-70 32-pin plcc a29l004atl-70f 32-pin pb-free plcc a29l004atx-70 32-pin stsop (8mm x 13.4mm) A29L004ATX-70F 32-pin pb-free stsop (8mm x 13.4mm) a29l004atv-70 32-pin tsop (8mm x 20mm) a29l004atv-70f 32-pin pb-free tsop (8mm x 20mm) a29l004atw-70 40-pin tsop a29l004atw-70f 40-pin pb-free tsop a29l004aty-70 32-pin stsop (8mm x 14mm) a29l004aty-70f 70 4 20 0.2 32-pin pb-free stsop (8mm x 14mm) a29l004atl-90 32-pin plcc a29l004atl-90f 32-pin pb-free plcc a29l004atx-90 32-pin stsop (8mm x 13.4mm) a29l004atx-90f 32-pin pb-free stsop (8mm x 13.4mm) a29l004atv-90 32-pin tsop (8mm x 20mm) a29l004atv-90f 32-pin pb-free tsop (8mm x 20mm) a29l004atw-90 40-pin tsop a29l004atw-90f 40-pin pb-free tsop a29l004aty-90 32-pin stsop (8mm x 14mm) a29l004aty-90f 90 4 20 0.2 32-pin pb-free stsop (8mm x 14mm)
a29l004a series preliminary (march, 2005, version 0.0) 33 amic technology, corp. bottom boot sector flash part no. access time (ns) active read current typ. (ma) program/erase current typ. (ma) standby current typ. ( a ) package a29l004aul-70 32-pin plcc a29l004aul-70f 32-pin pb-free plcc a29l004aux-70 32-pin stsop (8mm x 13.4mm) a29l004aux-70f 32-pin pb-free stsop (8mm x 13.4mm) a29l004auv-70 32-pin tsop (8mm x 20mm) a29l004auv-70f 32-pin pb-free tsop (8mm x 20mm) a29l004auw-70 40-pin tsop a29l004auw-70f 40-pin pb-free tsop a29l004auy-70 32-pin stsop (8mm x 14mm) a29l004auy-70f 70 4 20 0.2 32-pin pb-free stsop (8mm x 14mm) a29l004aul-90 32-pin plcc a29l004aul-90f 32-pin pb-free plcc a29l004aux-90 32-pin stsop (8mm x 13.4mm) a29l004aux-90f 32-pin pb-free stsop (8mm x 13.4mm) a29l004auv-90 32-pin tsop (8mm x 13.4mm) a29l004auv-90f 32-pin pb-free tsop (8mm x 13.4mm) a29l004auw-90 40-pin tsop a29l004auw-90f 40-pin pb-free tsop a29l004auy-90 32-pin stsop (8mm x 14mm) a29l004auy-90f 90 4 20 0.2 32-pin pb-free stsop (8mm x 14mm)
a29l004a series preliminary (march, 2005, version 0.0) 34 amic technology, corp. package information tsop 40l type i (10 x 20mm) outline dimensions unit: inches/mm detail "a" d 1 e d l c gage plane 0.25 e b d c 0.076 a a 2 a 1 pin1 seating plane dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.0067 0.0087 0.0106 0.17 0.22 0.27 c 0.004 - 0.0083 0.10 - 0.21 e 0.394 bsc 10.00 bsc e 0.020 bsc 0.50 bsc d 0.787 bsc 20.00 bsc d 1 0.724 bsc 18.40 bsc l 0.020 0.024 0.028 0.50 0.60 0.70 0 3 5 0 3 5 notes: 1. dimension d 1 and e do not include mold flash. 2. the lead width dimension do es not include dambar protrusion. total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius of the foot.
a29l004a series preliminary (march, 2005, version 0.0) 35 amic technology, corp. package information plcc 32l outline dimension unit: inches/mm a 1 a 2 a e d y h d d 13 g d b 1 b g e c 5 14 20 21 29 30 32 1 4 e h e l dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.134 - - 3.40 a 1 0.0185 - - 0.47 - - a 2 0.105 0.110 0.115 2.67 2.80 2.93 b 1 0.026 0.028 0.032 0.66 0.71 0.81 b 0.016 0.018 0.021 0.41 0.46 0.54 c 0.008 0.010 0.014 0.20 0.254 0.35 d 0.547 0.550 0.553 13.89 13.97 14.05 e 0.447 0.450 0.453 11.35 11.43 11.51 e 0.044 0.050 0.056 1.12 1.27 1.42 g d 0.490 0.510 0.530 12.45 12.95 13.46 g e 0.390 0.410 0.430 9.91 10.41 10.92 h d 0.585 0.590 0.595 14.86 14.99 15.11 h e 0.485 0.490 0.495 12.32 12.45 12.57 l 0.075 0.090 0.095 1.91 2.29 2.41 y - - 0.003 - - 0.075 0 - 10 0 - 10 notes: 1. dimensions d and e do not include resin fins. 2. dimensions g d & g e are for pc board surface mount pad pitch design reference only.
a29l004a series preliminary (march, 2005, version 0.0) 36 amic technology, corp. package information tsop 32l type i (8 x 20mm) outline dimensions unit: inches/mm e l e l a a 2 c d y detail "a" s a 1 b h d d e detail "a" dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.009 0.011 0.18 0.22 0.27 c 0.004 - 0.008 0.11 - 0.20 d 0.720 0.724 0.728 18.30 18.40 18.50 e - 0.315 0.319 - 8.00 8.10 e 0.020 bsc 0.50 bsc h d 0.779 0.787 0.795 19.80 20.00 20.20 l 0.016 0.020 0.024 0.40 0.50 0.60 l e - 0.032 - - 0.80 - s - - 0.020 - - 0.50 y - - 0.003 - - 0.08 0 - 5 0 - 5 notes: 1. the maximum value of dimension d includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash.
a29l004a series preliminary (march, 2005, version 0.0) 37 amic technology, corp. package information stsop 32l type i (8 x 13.4 mm) outline dimensions unit: inches/mm e detail "a" d 0.076mm detail "a" s b d 1 e d l e l a a 2 c a 1 seating plane dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.049 - - 1.25 a 1 0.002 - - 0.05 - - a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.007 0.008 0.009 0.17 0.20 0.23 c 0.0056 0.0059 0.0062 0.142 0.150 0.158 e 0.311 0.315 0.319 7.90 8.00 8.10 e 0.020 typ 0.50 typ d 0.520 0.528 0.535 13.20 13.40 13.60 d 1 0.461 0.465 0.469 11.70 11.80 11.90 l 0.012 0.020 0.028 0.30 0.50 0.70 l e 0.0275 0.0315 0.0355 0.700 0.800 0.900 s 0.0109 typ 0.278 typ 0 3 5 0 3 5 notes: 1. the maximum value of dimension d 1 includes end flash. 2. dimension e does not include resin fins. 3. dimension s includes end flash.
a29l004a series preliminary (march, 2005, version 0.0) 38 amic technology, corp. package information stsop 32l type i (8 x 14mm) outline dimensions unit: inches/mm e detail "a" detail "a" b d 1 e d l a a 2 c a 1 pin1 gage plane 0.254 d y dimensions in inches dimensions in mm symbol min nom max min nom max a - - 0.047 - - 1.20 a 1 0.002 - 0.006 0.05 - 0.15 a 2 0.037 0.039 0.041 0.95 1.00 1.05 b 0.0067 0.0087 0.0106 0.17 0.22 0.27 c 0.004 - 0.0083 0.10 - 0.21 e 0.311 0.315 0.319 7.90 8.00 8.10 e - 0.0197 - - 0.50 - d 0.543 0.551 0.559 13.80 14.00 14.20 d 1 0.484 0.488 0.492 12.30 12.40 12.50 l 0.020 0.024 0.028 0.50 0.60 0.70 y 0.000 - 0.003 0.00 - 0.076 0 3 5 0 3 5 notes: 1. dimension e does not include mold flash. 3. dimension d 1 does not include interlead flash. 4. dimension b does not in clude dambar protrusion.

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